module top_module (input a, input b, input c, output out);//

    wire	out_wire;
    
    andgate u_andgate_0(
        .out(out_wire),
        .a(a),
        .b(b),
        .c(c),
        .d(1'b1),
        .e(1'b1)
    );
    
    assign out = ~out_wire;

endmodule
